Various programmable logic architectures are known, including, for example, programmable logic devices ("PLD"), programmable logic arrays ("PLA") and programmable array logic ("PAL.TM."). Although there are many differences between the various architectures, each of the PLD, PLA, and PAL architectures typically includes a set of input conductors directly coupled as inputs to an array of logical AND gates ("product term array"), the outputs of which, in turn, act as inputs to another portion of the logic device.
FIG. 1 shows a conventional complex programmable logic device ("CPLD") 100 which includes a programmable interconnect matrix ("PIM") 110 and a number of logic blocks 120. Although eight logic blocks 120 are shown, other configurations of CPLD 100 may have as few as two logic blocks 120 or more than eight logic blocks 120. For the CPLD 100 shown in FIG. 1, a total of 262 inputs, each of which is connected to the PIM 110, are provided. PIM 110 is capable of providing each logic block 120 with its own set of input terms by independently selecting as many as 36 of the possible 262 input signals as input terms for each logic block 120. As shown, the logic complements for each of the 36 signals output by the PIM 110 are also provided to each logic block 120. Thus, each logic block 120 receives as many as 72 input terms from the PIM 110.
The PIM 110 includes a number of programmable elements (not shown) for controlling an array of multiplexers (not shown) to reduce the total number of programmable elements required. The programmable elements may be volatile memory elements such as static random access memory ("SRAM"), non-volatile memory elements such as flash electrically erasable programmable read-only memory ("Flash EEPROM"), fuses or anti-fuses. Alternatively, the programmable elements of the PIM 110 may be implemented to control a matrix of crosspoint switches. Such an implementation, however, increases the total number of programmable elements required to make the same number of connections. Whether the connections between input conductors and output conductors are provided by a crosspoint switch matrix or by an array of multiplexers, each output conductor can be connected to a maximum of one input conductor. Thus, both forms of connection perform a multiplexing function in the sense that both forms of connection provide for the selection of one input conductor from a set of many input conductors. Therefore, as used herein, the term multiplexer will be understood to encompass any circuit that performs a multiplexing function, regardless of the number of programmable elements required to control that circuit.
The 262 inputs to the PIM include 128 feedback signals, 128 input signals, and six dedicated input signals, which include four clock signals. Sixteen feedback signals and as many as 16 input signals are provided by each logic block 120. Each logic block 120 may be programmed to perform selected logic functions, for example using subcombinations of the 72 input terms provided by the PIM 110. Each logic block 120 has 16 input/output ("I/O") pins, which may be used as either inputs to the PIM 110 or outputs of the CPLD 100.
Conceptually, CPLD 100 may be regarded as a PIM coupled in series with eight PLDs coupled in parallel, wherein each logic block 120 corresponds to a single PLD. Intermediate stages in the outputs of each of the eight PLDs are fed back as inputs to the PIM. Depending on the particular set of input signals routed to the outputs of the PIM and the programmed logic functions for each logic block 120, the eight PLDs may, in fact, act as two or more PLDs coupled in series with each other. CPLD 100 thus provides a highly versatile logic device which may be implemented on a single semiconductor die.
FIG. 2 shows portions of CPLD 100 in greater detail. Specifically, logic block 120 is shown as including a product term array 210, a product term allocator 215, macrocells 220 and I/O cells 225. The product term array for this embodiment is a fully programmable AND array, although other implementations may be used. The product term allocator 215 allocates product terms from the product term array 210 to 16 macrocells 220. The product term allocator 215 "steers" product terms to macrocells as needed. For example, if one macrocell requires 10 product terms while another requires only three product terms, the product term allocator 215 steers 10 product terms to one macrocell and three product terms to the other macrocell. From 0 to 16 product terms can be steered to any one macrocell.
The outputs for each of the 16 macrocells 220 are fed back to the PIM 110 as input signals. This specific architecture of the macrocells 220 may be any appropriate architecture. The 16 outputs of the macrocells 220 are also fed to the 16 I/0 cells 225.
The output signals of the I/O cells 225 are fed back as input signals to the PIM 110 and are also provided to I/O pins.
FIG. 3 shows the product term allocation scheme within logic block 120 in more detail. As shown, signals from PIM 110 are applied to the product term array 210. Output signals from the product term array 210 are then provided to the product term allocator 215 which is shown in FIG. 3 as implementing a logic OR function. For each of the logic OR terms 310 of product term allocator 215, the output of that term is provided to one of the 16 macrocells 220. As shown, each logic OR function within product term allocator 215 may provide from 0 to 16 product terms from product term array 210 to each macrocell 220, although some of the product terms will be available to only one unique macrocell.
FIG. 4 shows this product term allocation scheme in more detail. In particular, FIG. 4 is a graphical illustration of the allocation of product terms to macrocells within programmable logic device 100. Along the top, the 80 product terms of product term array 210 are enumerated. The vertical axis represents the 16 macrocells 220 per logic block 120. Each logic OR term 310 provided by the product term allocator 215 is illustrated as providing up to 16 of the product terms to each macrocell. For example, macrocell 02 may be provided with product terms 10-25. Similarly, macrocell 11 may be provided with product terms 46-61. As indicated, however, product terms 00-05 are available only to macrocell 00 and product terms 74-79 are available only to macrocell 15. Each of the other product terms 06-73 is shared by at least two macrocells, for example macrocells 00 and 01 share product term 09, or up to four macrocells, for example, product terms 10-34 are shared by macrocells 05, 06, 07 and 08.
The product term allocation scheme illustrated in FIG. 4 is non-homogeneous in that some product terms can be provided to up to four macrocells while other product terms are available to only one macrocell. This causes a problem for routing software which is used to implement desired logic functions by programming CPLD 100. The routing software is limited in that if, for example, product terms 00 and 04 need to be provided to separate macrocells, the logic function which requires such an implementation cannot be fit to CPLD 100. Instead, those signals would have to be routed to different product terms which are available in different macrocells, thus leaving fewer overall product terms available for allocation. The overall result is that some logic functions simply will not be able to be fit in CPLD 100. Accordingly, what is desired is an improved product term allocation scheme.